<?xml version="1.0" encoding="UTF-8"?>
<metadata>
  <identifier>1995-mti-vsystem-vplus-modelsim-44g</identifier>
  <mediatype>software</mediatype>
  <collection>open_source_software</collection>
  <creator>Model Technology</creator>
  <date>1995-11-14</date>
  <description>&lt;div&gt;Archived from https://archive.org/details/Synthesis_Solutions_by_Exemplar_Logic_Exemplar_Logic. For Windows NT / SunOS / Solaris / HP-UX / AIX.&lt;/div&gt;&lt;div&gt;&lt;br /&gt;&lt;/div&gt;&lt;div&gt;===============================================================================&lt;/div&gt;&lt;div&gt;RELEASE NOTES FOR V-SYSTEM VHDL/Verilog Version 4.4g&lt;/div&gt;&lt;div&gt;(14 November 1995)&lt;/div&gt;&lt;div&gt;&lt;br /&gt;&lt;/div&gt;&lt;div&gt;(release notes for 4.4a, 4.4c, 4.4d, 4.4e and 4.4f follow)&lt;/div&gt;&lt;div&gt;&lt;br /&gt;&lt;/div&gt;&lt;div&gt;CHANGES:&lt;/div&gt;&lt;div&gt;========&lt;/div&gt;&lt;div&gt;&lt;br /&gt;&lt;/div&gt;&lt;div&gt;o Fixed memory leak in force/unforce commands&lt;/div&gt;&lt;div&gt;o Modified textio-read to deallocate lines after emptying them&lt;/div&gt;&lt;div&gt;o Fixed bug in memory management that occasionally caused crashes.&lt;/div&gt;&lt;div&gt;o Fixed Verilog index into net's on X or out-of-range indexes.&lt;/div&gt;&lt;div&gt;o Fixed Verilog $readmem to properly parse certain comments.&lt;/div&gt;&lt;div&gt;o Fixed Verilog `ifdef bug.&lt;/div&gt;&lt;div&gt;&lt;br /&gt;&lt;/div&gt;</description>
  <language>eng</language>
  <scanner>Internet Archive HTML5 Uploader 1.7.0</scanner>
  <subject>modelsim</subject>
  <title>Modeltech V-SYSTEM VHDL/Verilog 4.4g</title>
  <subject>modeltech</subject>
  <subject>vsystem</subject>
  <subject>vplus</subject>
  <uploader>beta_cai@webmail.hzau.edu.cn</uploader>
  <collection>community</collection>
  <publicdate>2022-11-15 15:17:36</publicdate>
  <addeddate>2022-11-15 15:17:36</addeddate>
  <curation>[curator]validator@archive.org[/curator][date]20221115152350[/date][comment]checked for malware[/comment]</curation>
</metadata>
